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Renesas Electronics /R7FA6T1AD /GPT32EH0 /GTPDBR

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Interpret as GTPDBR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0GTPDBR

Description

General PWM Timer Cycle Setting Double-Buffer Register

Fields

GTPDBR

Cycle Setting Double-Buffer Register

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data